1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method.
2. Description of the Related Art
As the nonvolatile memory that can store information after a power supply is turned off, the flash memory and the ferroelectric memory are known.
Out of them, the flash memory has a floating gate that is buried in a gate insulating film of an insulated-gate field effect transistor (IGFET), and stores information by accumulating a charge representing the stored information in this floating gate. However, such flash memory possesses a defect that, since a tunnel current must be supplied to the gate insulating film in writing or erasing the information, a relatively high voltage is required.
In contrast, the ferroelectric memory, called also FeRAM (Ferroelectric Random Access Memory), stores information by utilizing the hysteresis characteristic of a ferroelectric film that a ferroelectric capacitor includes. In this ferroelectric film, the polarization occurs in response to a voltage applied between an upper electrode and a lower electrode of the capacitor, and the spontaneous polarization still remains after the voltage is removed. This spontaneous polarization is reversed when the polarity of the applied voltage is reversed. Thus, the information can be written into the ferroelectric film by relating respective directions of the spontaneous polarization to “1” and “0”. The FeRAM has such advantages that a voltage required for the writing is lower than that in the flash memory and the information can be written at a higher rate than the flash memory.
In manufacturing such FeRAM, the annealings peculiar to the FeRAM, such as the crystallizing annealing for crystallizing the capacitor dielectric film, and the recovery annealing for recovering the capacitor dielectric film from the damage caused by etching or sputter, are performed. These annealings contribute to improve the ferroelectric characteristics of the capacitor dielectric film. However, portions other than the capacitor, e.g., a refractory metal sicilide layer on the source/drain region of a MOS transistor, suffers from an unnecessary heat load by these annealings, and hence there arises concern that the characteristics of the MOS transistor are deteriorated.
Need exists, therefore, to improve the characteristics of the capacitor dielectric film by optimizing the annealing conditions such as annealing time and annealing temperature, as well as suppressing the deterioration of the characteristics of the MOS transistor, in the steps of manufacturing the FeRAM.
Here, the technologies related to the present invention are set forth in following Patent Literatures 1 to 3.
In Patent Literature 1 among them, an upper surface of the cobalt silicide (CoSi) layer is covered with a metal film or the like, and then the RTA (Rapid Thermal Annealing) is applied in this condition. Thus, agglomeration of the cobalt silicide is prevented.
Also, in Patent Literature 2, a titanium layer is formed on the cobalt silicide layer, and then the cobalt silicide layer is annealed. Thus, titanium in the titanium layer is diffused into the cobalt silicide layer, so that the crystal structure of the cobalt silicide layer is stabilized.
Then, in Patent Literature 3, the annealing is applied to the capacitor dielectric film in the oxygen or ozone plasma atmosphere, thereby lowering the annealing temperature.                [Patent Literature 1] Patent Application Publication (KOKAI) 2003-347311        [Patent Literature 2] Patent Application Publication (KOKAI) 2003-303786        [Patent Literature 3] Japanese Patent Publication (KOKAI) Hei 6-21333        